Implementation and acceleration scheme of Heart sound classification Algorithm based on SOC-FPGA

ABSTRACT-Widespread screening of congenital heart disease is of time-consuming, labor-consuming, and difficult for rural doctors to master the skill of cardiac auscultation. A kind of machine-assisted diagnosis method was put forwarded in this paper to solve the above problems. In which a heart sound classification algorithm and acceleration plan of CNN was implemented on a small scale SoC-FPGA chip with fewer resources. In this method, heart sounds were denoised and segmented into cardio cycles first. Then STFT transformation was done for time-frequency feature extraction. The time-frequency features were used to train the CNN model to extract network model parameters. In hardware implementation, the parallelism of CNN was corresponding to FPGA parallel hardware. In order to make acceleration of the algorithm, loop unrolling, fixed-point of model parameter, and reducing global memory access were done. The experimental results show that the classification speed is 3.13 times as much as one of CPU at the same conditions with the classification accuracy not any dropping significantly. It provides an offline solution for the machine-assisted screening of congenital heart disease.