{"title":"基于fpga的任意波形发生器的设计与实现","authors":"Min Xu, J. Hu, Y. Gao","doi":"10.1109/ICCASE.2011.5997708","DOIUrl":null,"url":null,"abstract":"This paper proposed a solution for arbitrary waveform generator (AWG), in which integrated DDS chip is engaged as the essential frequency variable clock source. DACs are driven to generate the waveforms by clock signals, which are obtained from the reshaping and shape lifting of output from DDS by clock distributor. The data to build waveform up are stored in cache and loaded into DACs continuously by FPGA. An embedded process was set up in FPGA and would interpolate data from envelope when output of whole system is required to be typical reference. AGC circuits then standardize signal out of DACs to a constant peak-to-peak value, and VGA is obliged to fit the amplitude of signal as same as settings. Finally, the signal flow out this generator via BNC over filtering. In author's practice, a demo with performance of 200Msps rate and 100MHz above analog bandwidth can be achieved.","PeriodicalId":369749,"journal":{"name":"2011 International Conference on Control, Automation and Systems Engineering (CASE)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"FPGA-Based Design and Implementation of Arbitrary Waveform Generator\",\"authors\":\"Min Xu, J. Hu, Y. Gao\",\"doi\":\"10.1109/ICCASE.2011.5997708\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposed a solution for arbitrary waveform generator (AWG), in which integrated DDS chip is engaged as the essential frequency variable clock source. DACs are driven to generate the waveforms by clock signals, which are obtained from the reshaping and shape lifting of output from DDS by clock distributor. The data to build waveform up are stored in cache and loaded into DACs continuously by FPGA. An embedded process was set up in FPGA and would interpolate data from envelope when output of whole system is required to be typical reference. AGC circuits then standardize signal out of DACs to a constant peak-to-peak value, and VGA is obliged to fit the amplitude of signal as same as settings. Finally, the signal flow out this generator via BNC over filtering. In author's practice, a demo with performance of 200Msps rate and 100MHz above analog bandwidth can be achieved.\",\"PeriodicalId\":369749,\"journal\":{\"name\":\"2011 International Conference on Control, Automation and Systems Engineering (CASE)\",\"volume\":\"85 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-07-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 International Conference on Control, Automation and Systems Engineering (CASE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCASE.2011.5997708\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 International Conference on Control, Automation and Systems Engineering (CASE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCASE.2011.5997708","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
FPGA-Based Design and Implementation of Arbitrary Waveform Generator
This paper proposed a solution for arbitrary waveform generator (AWG), in which integrated DDS chip is engaged as the essential frequency variable clock source. DACs are driven to generate the waveforms by clock signals, which are obtained from the reshaping and shape lifting of output from DDS by clock distributor. The data to build waveform up are stored in cache and loaded into DACs continuously by FPGA. An embedded process was set up in FPGA and would interpolate data from envelope when output of whole system is required to be typical reference. AGC circuits then standardize signal out of DACs to a constant peak-to-peak value, and VGA is obliged to fit the amplitude of signal as same as settings. Finally, the signal flow out this generator via BNC over filtering. In author's practice, a demo with performance of 200Msps rate and 100MHz above analog bandwidth can be achieved.