双核高摆幅c类振荡器,超低相位噪声

Massoud Tohidian, Seyed Amir Reza Ahmadi Mehr, R. Bogdan
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引用次数: 22

摘要

我们提出了一种超低相位噪声振荡器拓扑结构,其工作前提是耦合第二个相同的振荡器核心将使总体相位噪声降低3 dB。对于每个核心,使用高摆幅c类振荡器来实现最低的相位噪声。所实现的振荡器在4.07-4.91 GHz范围内可调,从2.15 V电源吸收39-59 mA。测量到的相位噪声分别为-146.7 dBc/Hz和-163.1 dBc/Hz,分别来自4.07 GHz载波,偏移量为3 MHz和20 MHz。这是批量CMOS IC中报道的最低相位噪声。该相位噪声符合GSM900普通基站接收器和移动站发射机标准,这些标准在蜂窝通信中具有最严格的相位噪声要求。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Dual-core high-swing class-C oscillator with ultra-low phase noise
We propose an ultra-low phase noise oscillator topology that works on the premise that coupling a second identical oscillator core would reduce the overall phase noise by 3 dB. For each core, a high-swing class-C oscillator is used to achieve the lowest phase noise. The realized oscillator is tunable from 4.07-4.91 GHz, drawing 39-59 mA from a 2.15 V power supply. The measured phase noise is -146.7 dBc/Hz and -163.1 dBc/Hz at 3 MHz and 20 MHz offset, respectively, from 4.07 GHz carrier. This is the lowest ever reported phase noise in bulk CMOS IC. This phase noise meets GSM900 normal basestation receiver and mobile station transmitter standards, which have the toughest phase noise requirements in cellular communications.
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