{"title":"216GHz 0.5mW发射机，采用65nm CMOS，采用紧凑型功率组合器","authors":"Sriram Muralidharan, Kefei Wu, M. Hella","doi":"10.1109/APMC.2015.7413041","DOIUrl":null,"url":null,"abstract":"This paper presents the design and measurements of a 216GHz, 0.5mW transmitter using 65nm bulk CMOS process. The transmitter is formed of an amplifier-multiplier chain, where the power amplifier delivers a Psat =16dBm at 110GHz to a passive frequency doubler. The PA stage employs a novel single-ended to 2-way differential power combiner based on vertically coupled transmission lines. A passive frequency doubler implemented using MOS varactors follows the PA. The 216GHz transmitter delivers a maximum of 0.5mW at 216GHz with a 2.8% bandwidth, while consuming 500mW from a 1V DC supply. The chip, implemented in thin BEOL seven metal ST-65nm CMOS process, occupies a total area of 0.88mm2.","PeriodicalId":269888,"journal":{"name":"2015 Asia-Pacific Microwave Conference (APMC)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A 216GHz 0.5mW transmitter with a compact power combiner in 65nm CMOS\",\"authors\":\"Sriram Muralidharan, Kefei Wu, M. Hella\",\"doi\":\"10.1109/APMC.2015.7413041\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design and measurements of a 216GHz, 0.5mW transmitter using 65nm bulk CMOS process. The transmitter is formed of an amplifier-multiplier chain, where the power amplifier delivers a Psat =16dBm at 110GHz to a passive frequency doubler. The PA stage employs a novel single-ended to 2-way differential power combiner based on vertically coupled transmission lines. A passive frequency doubler implemented using MOS varactors follows the PA. The 216GHz transmitter delivers a maximum of 0.5mW at 216GHz with a 2.8% bandwidth, while consuming 500mW from a 1V DC supply. The chip, implemented in thin BEOL seven metal ST-65nm CMOS process, occupies a total area of 0.88mm2.\",\"PeriodicalId\":269888,\"journal\":{\"name\":\"2015 Asia-Pacific Microwave Conference (APMC)\",\"volume\":\"94 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 Asia-Pacific Microwave Conference (APMC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APMC.2015.7413041\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 Asia-Pacific Microwave Conference (APMC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APMC.2015.7413041","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 216GHz 0.5mW transmitter with a compact power combiner in 65nm CMOS
This paper presents the design and measurements of a 216GHz, 0.5mW transmitter using 65nm bulk CMOS process. The transmitter is formed of an amplifier-multiplier chain, where the power amplifier delivers a Psat =16dBm at 110GHz to a passive frequency doubler. The PA stage employs a novel single-ended to 2-way differential power combiner based on vertically coupled transmission lines. A passive frequency doubler implemented using MOS varactors follows the PA. The 216GHz transmitter delivers a maximum of 0.5mW at 216GHz with a 2.8% bandwidth, while consuming 500mW from a 1V DC supply. The chip, implemented in thin BEOL seven metal ST-65nm CMOS process, occupies a total area of 0.88mm2.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
