M. Iwabuchi, M. Usami, M. Kashiyama, Takashi Oomori, Shigeharu Murata, T. Hiramoto, T. Hashimoto, Yasuhiro Nakajima
{"title":"一个1.5 ns周期时间18kb伪双端口RAM","authors":"M. Iwabuchi, M. Usami, M. Kashiyama, Takashi Oomori, Shigeharu Murata, T. Hiramoto, T. Hashimoto, Yasuhiro Nakajima","doi":"10.1109/VLSIC.1993.920565","DOIUrl":null,"url":null,"abstract":"High-speed memories have been used in computers for buffer memory. Such a memory is interconnected with a high-speed arithmetic unit, and the operation cycle-time of memory dominates the performance of computer. Moreover, in order to expand data throughput, it is very advantageous for a high-speed cycle memory to provide a dual-port RAM function, that enables read and write simultaneously. In this paper, a pseudo-dual-port RAM with a 1.5 ns operation cycle is reported. The chip contains 18 kbit RAM (256word x 9bit x 8block) and 9k-gate peripheral logic gates operating during 1.5 ns cycle-time. It is fabricated by a double polysilicon self-aligned bipolar process, using SOI wafer and trench isolation.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A 1.5 ns cycle-time 18 kb pseudo-dual-port RAM\",\"authors\":\"M. Iwabuchi, M. Usami, M. Kashiyama, Takashi Oomori, Shigeharu Murata, T. Hiramoto, T. Hashimoto, Yasuhiro Nakajima\",\"doi\":\"10.1109/VLSIC.1993.920565\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"High-speed memories have been used in computers for buffer memory. Such a memory is interconnected with a high-speed arithmetic unit, and the operation cycle-time of memory dominates the performance of computer. Moreover, in order to expand data throughput, it is very advantageous for a high-speed cycle memory to provide a dual-port RAM function, that enables read and write simultaneously. In this paper, a pseudo-dual-port RAM with a 1.5 ns operation cycle is reported. The chip contains 18 kbit RAM (256word x 9bit x 8block) and 9k-gate peripheral logic gates operating during 1.5 ns cycle-time. It is fabricated by a double polysilicon self-aligned bipolar process, using SOI wafer and trench isolation.\",\"PeriodicalId\":127467,\"journal\":{\"name\":\"Symposium 1993 on VLSI Circuits\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-05-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Symposium 1993 on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1993.920565\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Symposium 1993 on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1993.920565","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
摘要
高速存储器已在计算机中用作缓冲存储器。这种存储器与高速算术单元相互连接，存储器的运算周期时间支配着计算机的性能。此外，为了扩大数据吞吐量，提供双端口RAM功能的高速循环存储器是非常有利的，可以同时读取和写入。本文报道了一种工作周期为1.5 ns的伪双端口RAM。该芯片包含18kbit RAM (256word x 9bit x 8block)和9k门外设逻辑门，工作周期为1.5 ns。它是采用SOI晶圆和沟槽隔离的双多晶硅自对准双极工艺制造的。
High-speed memories have been used in computers for buffer memory. Such a memory is interconnected with a high-speed arithmetic unit, and the operation cycle-time of memory dominates the performance of computer. Moreover, in order to expand data throughput, it is very advantageous for a high-speed cycle memory to provide a dual-port RAM function, that enables read and write simultaneously. In this paper, a pseudo-dual-port RAM with a 1.5 ns operation cycle is reported. The chip contains 18 kbit RAM (256word x 9bit x 8block) and 9k-gate peripheral logic gates operating during 1.5 ns cycle-time. It is fabricated by a double polysilicon self-aligned bipolar process, using SOI wafer and trench isolation.
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