带耦合电感的隔离准z源无桥功率因数校正

Q. Nha, H. Chiu, Yu-Kang Lo, Pham Phu Hieu, M. Alam
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引用次数: 1

摘要

隔离型功率因数校正变换器的导通路径上存在慢恢复二极管,导致导通损耗。本研究提出了一种新的PFC应用拓扑,即隔离型准z源无桥PFC变换器,通过消除导通路径上的低恢复二极管来提高效率。采用非耗散箝位结构,可以完全吸收寄生元件之间共振引起的mosfet上的电压尖峰。因此,使用低Rds(ON)的低压mosfet来降低传导损耗。此外,利用耦合电感减小升压电感的尺寸。本文对输入180 ~ 240v,输出400v / 1kw的仿真电路进行了验证,验证了其可行性。仿真结果表明,mosfet上的尖峰效应完全消除。输入电流为正弦波,且与输入电压同相。该拓扑结构具有高效率、高功率因数和低电流总谐波畸变的应用前景。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Isolated quasi z-source bridgeless power factor correction with coupled inductor
Existence of slow-recovery diodes on conduction paths of the isolated power factor correction converters causes conduction losses. This study proposes a new topology for PFC applications, namely isolated quasi z-source bridgeless PFC converter, to improve efficiency by eliminating of the low-recovery diodes on the conduction paths. The voltage spikes on MOSFETs caused by resonance between parasitic components are completely absorbed by using a non-dissipative clamping structure. As a result, low-voltage MOSFETs with low Rds(ON) are used to reduce the conduction loss. Moreover, couple-inductor is utilized to reduce the size of the boost-inductor. In this paper, a simulation circuit with 180-240 V input, 400 V/1 kW output was verified to demonstrate its feasibility. The simulation results shown the spikes on MOSFETs were absolutely eliminated. The input current was sinusoidal and in phase with the input voltage. The proposed topology is promising for high efficiency, high power factor, and low current total harmonic distortion applications.
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