{"title":"时间戳方法使用降低成本的ADC硬件","authors":"T. Lyons","doi":"10.1109/TEST.2009.5355736","DOIUrl":null,"url":null,"abstract":"For many semiconductor devices, time stability and relative time location of electrical events is critical; clocks need to strobe data when the data is valid. This fundamental performance is indicative of both the general quality of manufacture and the suitability of a particular device. Parametric measures might include duty cycle variation, peak-to-peak jitter, RMS jitter and minimum pulse width. As increasingly complex timing generation circuits are implemented with mixed analog and digital technology, more sophisticated testing requires a time sense between events (e.g. cycle-to-cycle jitter, period jitter and deterministic jitter.)","PeriodicalId":419063,"journal":{"name":"2009 International Test Conference","volume":"74 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A timestamping method using reduced cost ADC hardware\",\"authors\":\"T. Lyons\",\"doi\":\"10.1109/TEST.2009.5355736\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"For many semiconductor devices, time stability and relative time location of electrical events is critical; clocks need to strobe data when the data is valid. This fundamental performance is indicative of both the general quality of manufacture and the suitability of a particular device. Parametric measures might include duty cycle variation, peak-to-peak jitter, RMS jitter and minimum pulse width. As increasingly complex timing generation circuits are implemented with mixed analog and digital technology, more sophisticated testing requires a time sense between events (e.g. cycle-to-cycle jitter, period jitter and deterministic jitter.)\",\"PeriodicalId\":419063,\"journal\":{\"name\":\"2009 International Test Conference\",\"volume\":\"74 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 International Test Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TEST.2009.5355736\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Test Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.2009.5355736","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A timestamping method using reduced cost ADC hardware
For many semiconductor devices, time stability and relative time location of electrical events is critical; clocks need to strobe data when the data is valid. This fundamental performance is indicative of both the general quality of manufacture and the suitability of a particular device. Parametric measures might include duty cycle variation, peak-to-peak jitter, RMS jitter and minimum pulse width. As increasingly complex timing generation circuits are implemented with mixed analog and digital technology, more sophisticated testing requires a time sense between events (e.g. cycle-to-cycle jitter, period jitter and deterministic jitter.)