{"title":"没有人是完美的:从参数化的实时场景中进行交互式合成","authors":"H. Giese, Stefan Henkler, M. Hirsch, F. Klein","doi":"10.1145/1138953.1138967","DOIUrl":null,"url":null,"abstract":"As technical systems keep growing more complex and sophisticated, designing software for the safety-critical coordination between their components becomes increasingly difficult. Verifying and correcting these components already represents a significant part of the development process both with respect to time and cost. Scenario-based synthesis has been put forward as an approach to accelerate the transition from requirements to a correct, verified model. In (8), we have presented a synthesis technique for deriving pattern behavior from a set of timed scenarios with parametrized time constraints. The derived patterns can then be verified using our technique for the compositional formal verification of Mechatronic UML models as introduced in (10). In this paper, we argue that the practical relevance of a synthesis technique predominantly depends rather on its ability to identify and point to specification errors than the complexity of the scenarios it could, in theory, process, provided with a correct specification. By means of a case study, we introduce the different types of specification errors that may arise during synthesis. Using our tools for modeling, synthesis, and verification, we then show how we can identify and resolve these errors in the successive phases of an interactive development process.","PeriodicalId":151927,"journal":{"name":"International Workshop on Scenarios and state machines: models, algorithms, and tools","volume":"74 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Nobody's perfect: interactive synthesis from parametrized real-time scenarios\",\"authors\":\"H. Giese, Stefan Henkler, M. Hirsch, F. Klein\",\"doi\":\"10.1145/1138953.1138967\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"As technical systems keep growing more complex and sophisticated, designing software for the safety-critical coordination between their components becomes increasingly difficult. Verifying and correcting these components already represents a significant part of the development process both with respect to time and cost. Scenario-based synthesis has been put forward as an approach to accelerate the transition from requirements to a correct, verified model. In (8), we have presented a synthesis technique for deriving pattern behavior from a set of timed scenarios with parametrized time constraints. The derived patterns can then be verified using our technique for the compositional formal verification of Mechatronic UML models as introduced in (10). In this paper, we argue that the practical relevance of a synthesis technique predominantly depends rather on its ability to identify and point to specification errors than the complexity of the scenarios it could, in theory, process, provided with a correct specification. By means of a case study, we introduce the different types of specification errors that may arise during synthesis. Using our tools for modeling, synthesis, and verification, we then show how we can identify and resolve these errors in the successive phases of an interactive development process.\",\"PeriodicalId\":151927,\"journal\":{\"name\":\"International Workshop on Scenarios and state machines: models, algorithms, and tools\",\"volume\":\"74 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-05-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Workshop on Scenarios and state machines: models, algorithms, and tools\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/1138953.1138967\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Workshop on Scenarios and state machines: models, algorithms, and tools","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1138953.1138967","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Nobody's perfect: interactive synthesis from parametrized real-time scenarios
As technical systems keep growing more complex and sophisticated, designing software for the safety-critical coordination between their components becomes increasingly difficult. Verifying and correcting these components already represents a significant part of the development process both with respect to time and cost. Scenario-based synthesis has been put forward as an approach to accelerate the transition from requirements to a correct, verified model. In (8), we have presented a synthesis technique for deriving pattern behavior from a set of timed scenarios with parametrized time constraints. The derived patterns can then be verified using our technique for the compositional formal verification of Mechatronic UML models as introduced in (10). In this paper, we argue that the practical relevance of a synthesis technique predominantly depends rather on its ability to identify and point to specification errors than the complexity of the scenarios it could, in theory, process, provided with a correct specification. By means of a case study, we introduce the different types of specification errors that may arise during synthesis. Using our tools for modeling, synthesis, and verification, we then show how we can identify and resolve these errors in the successive phases of an interactive development process.