Power-efficient value speculation for high-performance microprocessors

Improving instruction-level parallelism (ILP) has become one of the greatest challenges in high-performance microprocessor design. Several techniques for counteracting control and data dependencies, based on prediction and speculative execution, have been proposed and their cost-performance tradeoffs have been widely studied. However, in some cases, such as value speculation, power consumption considerations have remained unanalyzed. In this paper, we explore the main sources of power dissipation to be considered when value speculation is used, and we propose solutions to reduce this dissipation-reducing the size of the prediction tables, decreasing the amount of extra work due to speculative execution, and reducing the complexity of the out-of-order issue logic-in order to prove that value speculation can be considered a power-efficient technique for future generations of microprocessors.