T. Schwarzer, J. Falk, M. Glaß, J. Teich, C. Zebelein, C. Haubelt
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引用次数: 11
摘要
使用动态数据流图的应用程序建模非常适合多核平台。但是,应用程序的细粒度和平台之间经常存在不匹配。根据平台定制这种粒度,可以通过(a)减少动态调度开销和(b)利用编译器优化来实现性能提升。在本文中,我们提出了一种吞吐量优化的编译方法,该方法使用准静态调度(qss)来组合静态数据流子图的参与者。我们提出的方法在设计空间探索(Design Space Exploration, DSE)中结合了核心分配、qss和参与者绑定,优化了许多可用核心的吞吐量。在DSE期间,每个候选实现都被编译并在目标硬件上进行评估——这里是Intel i7和ARM Cortex-A9。包括合成基准测试和现实世界控制应用在内的实验结果表明,我们提出的整体编译方法优于不可知QSS的经典DSE以及采用QSS作为后处理步骤的DSE。其中,我们展示了一个案例,其中编译方法在4核实现中获得了9.91 x的加速,而经典的DSE只获得了2.12 x的加速。
Throughput-optimizing Compilation of Dataflow Applications for Multi-Cores using Quasi-Static Scheduling
Application modeling using dynamic dataflow graphs is well-suited for multi-core platforms. However, there is often a mismatch between the fine granularity of the application and the platform. Tailoring this granularity to the platform promises performance gains by (a) reducing dynamic scheduling overhead and (b) exploiting compiler optimizations. In this paper, we propose a throughput-optimizing compilation approach that uses Quasi-Static Schedules (QSSs) to combine actors of static dataflow subgraphs. Our proposed approach combines core allocation, QSSs, and actor binding in a Design Space Exploration (DSE), optimizing the throughput for a number of available cores. During the DSE, each implementation candidate is compiled to and evaluated on the target hardware---here an Intel i7 and an ARM Cortex-A9. Experimental results including synthetic benchmarks as well as a real-world control application show that our proposed holistic compilation approach outperforms classic DSEs that are agnostic of QSS as well as a DSE that employs QSS as a post-processing step. Amongst others, we show a case where the compilation approach obtains a speedup of 9.91 x for a 4-core implementation, while a classic DSE only obtains a speedup of 2.12 x.