A quantization error minimization using DDS-DAC for wideband fractional-N frequency synthesizer

This work presents a quantization error minimization technique for a fractional-N frequency synthesizer. By using a direct digital synthesis phase accumulator as the fractional divider and a DAC as pulse conversion, the quantization error can be much smaller than the one by conventional Σ-Δ modulated multi-modulus divider. With small quantization error, dedicated compensation mechanism is no longer necessary for wide loop bandwidth applications. To demonstrate this concept, a prototype chip is realized with the 0.18μm CMOS. The synthesizer consumes 31mA under a single 1.8V supply. With 1MHz closed-loop bandwidth, the in-band noise is −94dBc/Hz and the 3MHz offset noise is −118dBc/Hz for the 1.8GHz output. The output exhibits 27dB phase noise reduction. The settling time is 2μs under a 35MHz frequency step.