{"title":"具有位串行操作的脉冲编码神经网络硬件数字框架","authors":"Tim Kaulmann, Deniz Dikmen, U. Rückert","doi":"10.1109/HIS.2007.24","DOIUrl":null,"url":null,"abstract":"This publication presents a digital framework for building up pulse coded neural networks with leaky integrate-and-fire neurons and static synapses as well as dynamic synapses. The system, including a novel communication infrastructure, is mainly focused on ASIC synthesis but also shows a small footprint on Virtex2(Pro) FPGAs. Its bit-serial operation has been verified by simulations.","PeriodicalId":359991,"journal":{"name":"7th International Conference on Hybrid Intelligent Systems (HIS 2007)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A Digital Framework for Pulse Coded Neural Network Hardware with Bit-Serial Operation\",\"authors\":\"Tim Kaulmann, Deniz Dikmen, U. Rückert\",\"doi\":\"10.1109/HIS.2007.24\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This publication presents a digital framework for building up pulse coded neural networks with leaky integrate-and-fire neurons and static synapses as well as dynamic synapses. The system, including a novel communication infrastructure, is mainly focused on ASIC synthesis but also shows a small footprint on Virtex2(Pro) FPGAs. Its bit-serial operation has been verified by simulations.\",\"PeriodicalId\":359991,\"journal\":{\"name\":\"7th International Conference on Hybrid Intelligent Systems (HIS 2007)\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-09-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"7th International Conference on Hybrid Intelligent Systems (HIS 2007)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HIS.2007.24\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"7th International Conference on Hybrid Intelligent Systems (HIS 2007)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HIS.2007.24","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Digital Framework for Pulse Coded Neural Network Hardware with Bit-Serial Operation
This publication presents a digital framework for building up pulse coded neural networks with leaky integrate-and-fire neurons and static synapses as well as dynamic synapses. The system, including a novel communication infrastructure, is mainly focused on ASIC synthesis but also shows a small footprint on Virtex2(Pro) FPGAs. Its bit-serial operation has been verified by simulations.