Adding instruction cache effect to an exact schedulability analysis of preemptive real-time systems

Cache memories are commonly avoided in real-time systems because of their unpredictable behavior. Recently, some research has been done to obtain tighter bounds on the worst case execution time (WCET) of cached programs. These techniques usually assume a non preemptive underlying system. However, some techniques can be applied to allow the use of caches in preemptive systems. This paper describes how to incorporate the effect of instruction cache to the Response Time schedulability Analysis (RTA). RTA is an efficient analysis for preemptive fixed priority schedulers. We also compare through simulations the results of such an approach to the previously available CRMA (Cached RMA: cache effect is incorporated in the utilization based Rate Monotonic schedulability analysis). The results show that the cached version of RTA (CRTA) clearly outperforms CRMA.