使用硬宏测试逻辑资源的一种新的BIST方法

2008 International Conference on Neural Networks and Signal Processing Pub Date : 2008-06-07 DOI:10.1109/ICNNSP.2008.4590376

Zhiquan Zhang, Zhiping Wen, Lei Chen, Fan Zhang, Tao Zhou

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引用次数: 3

摘要

本文探讨了一种新的内置自检(BIST)方法，使用硬宏测试Xilinx Virtex fpga的可配置逻辑块(clb)。该方法可以完全检测和诊断clb中的单个和多个卡在门级故障以及相关信号线，同时显着减少了ora需要比较的输出。在使用扫描链方法检索BIST结果时，只需要两个会话的总共24个测试配置。

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A novel BIST approach for testing logic resources using Hard Macro

This paper explores an new Built-In Self-Test (BIST) approach to test the configurable logic blocks (CLBs) of Xilinx Virtex FPGAs using Hard Macro. The proposed approach completely detects and diagnoses single and multiple stuck-at gate-level faults as well as associated signal lines in the CLBs, while significantly reducing the Outputs needed to be compared by ORAs. Only 24 total test configurations for two sessions are required while retrieving the BIST results using scan chain method.

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2008 International Conference on Neural Networks and Signal Processing

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