{"title":"JLT离子/离合比对结构参数敏感性的研究","authors":"Madhabi Ganguly, Subhro Ghosal, D. Ghosh","doi":"10.1109/EDKCON.2018.8770477","DOIUrl":null,"url":null,"abstract":"As channel lengths are scaled down to the sub-30nm regime for improved performance and cost per function, the conventional Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET) would require super-steep doping profiles at the sourcechannel and channel-drain junctions to satisfy parametric constraints. Device architectures that do not have any junctions in the source-channel-drain path will therefore be of interest for scaling to ultra-short channel lengths. The Junction-less transistor, comprised of an isolated ultra-thin highly-doped device layer whose volume is fully depleted in the OFF state and is around flat- band in the ON state, is one such device. Such a structure overcomes the stringent technological requirement of an ultra-sharp grading profile required for nano-scale MOSFETs. A key factor determining the effectiveness of such nano-scale devices is their effectiveness as a switch for which the ION/IOFF ratio is a critical parameter. In this work we have studied the relative sensitivity of the ION/IOFF ratio to variations in several structural parameters of the device namely channel width, and composition of the dielectric layer, material composition of the channel region (i.e. Si vis-à-vis SiGe), doping concentration of the channel region, non-uniformity in the doping profile etc. We demonstrate through device simulations that replacement of Si with Si-Ge leads to an improvement in performance. The most notable change has been observed by using a vertically graded doping profile as opposed to the original proposed uniformly doped channel.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Study on Sensitivity of ION/IOFF Ratio of JLT to Structural Parameters\",\"authors\":\"Madhabi Ganguly, Subhro Ghosal, D. Ghosh\",\"doi\":\"10.1109/EDKCON.2018.8770477\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"As channel lengths are scaled down to the sub-30nm regime for improved performance and cost per function, the conventional Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET) would require super-steep doping profiles at the sourcechannel and channel-drain junctions to satisfy parametric constraints. Device architectures that do not have any junctions in the source-channel-drain path will therefore be of interest for scaling to ultra-short channel lengths. The Junction-less transistor, comprised of an isolated ultra-thin highly-doped device layer whose volume is fully depleted in the OFF state and is around flat- band in the ON state, is one such device. Such a structure overcomes the stringent technological requirement of an ultra-sharp grading profile required for nano-scale MOSFETs. A key factor determining the effectiveness of such nano-scale devices is their effectiveness as a switch for which the ION/IOFF ratio is a critical parameter. In this work we have studied the relative sensitivity of the ION/IOFF ratio to variations in several structural parameters of the device namely channel width, and composition of the dielectric layer, material composition of the channel region (i.e. Si vis-à-vis SiGe), doping concentration of the channel region, non-uniformity in the doping profile etc. We demonstrate through device simulations that replacement of Si with Si-Ge leads to an improvement in performance. The most notable change has been observed by using a vertically graded doping profile as opposed to the original proposed uniformly doped channel.\",\"PeriodicalId\":344143,\"journal\":{\"name\":\"2018 IEEE Electron Devices Kolkata Conference (EDKCON)\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE Electron Devices Kolkata Conference (EDKCON)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDKCON.2018.8770477\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDKCON.2018.8770477","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Study on Sensitivity of ION/IOFF Ratio of JLT to Structural Parameters
As channel lengths are scaled down to the sub-30nm regime for improved performance and cost per function, the conventional Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET) would require super-steep doping profiles at the sourcechannel and channel-drain junctions to satisfy parametric constraints. Device architectures that do not have any junctions in the source-channel-drain path will therefore be of interest for scaling to ultra-short channel lengths. The Junction-less transistor, comprised of an isolated ultra-thin highly-doped device layer whose volume is fully depleted in the OFF state and is around flat- band in the ON state, is one such device. Such a structure overcomes the stringent technological requirement of an ultra-sharp grading profile required for nano-scale MOSFETs. A key factor determining the effectiveness of such nano-scale devices is their effectiveness as a switch for which the ION/IOFF ratio is a critical parameter. In this work we have studied the relative sensitivity of the ION/IOFF ratio to variations in several structural parameters of the device namely channel width, and composition of the dielectric layer, material composition of the channel region (i.e. Si vis-à-vis SiGe), doping concentration of the channel region, non-uniformity in the doping profile etc. We demonstrate through device simulations that replacement of Si with Si-Ge leads to an improvement in performance. The most notable change has been observed by using a vertically graded doping profile as opposed to the original proposed uniformly doped channel.