Implementation of PFSCL razor flipflop

In this paper, a Razor flipflop is implemented using three different methods based on Positive Feedback Source Coupled Logic (PFSCL); universal gates, triple-tail cell and tristate buffer. The performance of the proposed methods is differentiated on the basis of power consumption, propagation delay, area and power-delay product. It has been concluded that the architecture based on triple-tail cell performed better in terms of power consumption by 66.67% while tristate buffer based architecture outperformed the other methods in terms of propagation delay by 60.23%. The tristate buffer based architecture also requires the least overhead area among the three proposed methods. The propagation delays of the three methods have been observed at various frequencies. While the propagation delay of universal gates based method increases with increasing frequency, the propagation delay of the other two methods do not vary with changing frequencies. This makes the triple-tail cell based and tristate buffer based method suitable for operation at high frequencies. The results have been verified through SPICE simulations using 0.18 micrometer CMOS technology parameters.