X. Lai, Kaipei Zhang, Chen Liu, Yuheng Wang, Longjie Zhong, Jiangtao Wang, Qiang Ye, Dejun Ma
{"title":"用于高精度全差分开关电容读出电路的多相时钟发生器","authors":"X. Lai, Kaipei Zhang, Chen Liu, Yuheng Wang, Longjie Zhong, Jiangtao Wang, Qiang Ye, Dejun Ma","doi":"10.1109/EDSSC.2017.8126559","DOIUrl":null,"url":null,"abstract":"In this paper, a non-overlap clock (NVC) generator for high accuracy fully differential Switched Capacitor (SC) readout circuit which is applied in Micro-Electro Mechanical System (MEMS) differential sensor is proposed. Compared with traditional generator, generating a set of non-overlap clock, this circuit generates a new set of clocks which are being nested inside the primary non-overlap clocks, and is driven by these clocks. The influence of charge injection of readout is reduced and thus its accuracy is improved. For more complex switched capacitor circuits, functional extension can be achieved only with logical combination. This generator is stimulated in a commercial 180nm CMOS process in SPICE. The simulation results show that accuracy of SC circuit is increased by 8.5%.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A multi-phase clock generator for high accuracy fully differential switched capacitor readout circuit\",\"authors\":\"X. Lai, Kaipei Zhang, Chen Liu, Yuheng Wang, Longjie Zhong, Jiangtao Wang, Qiang Ye, Dejun Ma\",\"doi\":\"10.1109/EDSSC.2017.8126559\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a non-overlap clock (NVC) generator for high accuracy fully differential Switched Capacitor (SC) readout circuit which is applied in Micro-Electro Mechanical System (MEMS) differential sensor is proposed. Compared with traditional generator, generating a set of non-overlap clock, this circuit generates a new set of clocks which are being nested inside the primary non-overlap clocks, and is driven by these clocks. The influence of charge injection of readout is reduced and thus its accuracy is improved. For more complex switched capacitor circuits, functional extension can be achieved only with logical combination. This generator is stimulated in a commercial 180nm CMOS process in SPICE. The simulation results show that accuracy of SC circuit is increased by 8.5%.\",\"PeriodicalId\":163598,\"journal\":{\"name\":\"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)\",\"volume\":\"49 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDSSC.2017.8126559\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2017.8126559","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A multi-phase clock generator for high accuracy fully differential switched capacitor readout circuit
In this paper, a non-overlap clock (NVC) generator for high accuracy fully differential Switched Capacitor (SC) readout circuit which is applied in Micro-Electro Mechanical System (MEMS) differential sensor is proposed. Compared with traditional generator, generating a set of non-overlap clock, this circuit generates a new set of clocks which are being nested inside the primary non-overlap clocks, and is driven by these clocks. The influence of charge injection of readout is reduced and thus its accuracy is improved. For more complex switched capacitor circuits, functional extension can be achieved only with logical combination. This generator is stimulated in a commercial 180nm CMOS process in SPICE. The simulation results show that accuracy of SC circuit is increased by 8.5%.