Design of combinational logic digital circuits using a mixed logic synthesis method

Themaincontribution ofthis paperisthe proposition ofa technology independent low powersynthesis procedure atthelogic (gate) level forcombinational logic digital CMOS circuits without reconvergent fan-out nodes, implementing Adjacent and/or Non-Adjacent Boolean functions. While manypapers havebeen published describing power-saving techniques, trade-off's between thedifferent design metrics arerarely discussed. Inthis paper, this issue is beingaddressed bymeansofa combined optimization parameter viz, Figure ofMerit (FoM), forevaluating thequality oflogic circuits designed. Thegoalistodecrease thepower consumption andsimultaneously improve the overall FigureofMerit. Sincethepower dissipated bya combinational logic circuit is mainly dictated bytheswitching activities ofall signals associated withthecircuit, themain focus hasbeenonreducing thesignal activities to theminimallevelrequired. A novel mathematical formulation hasalsobeen developed foraunique classification ofgates. Experimental results obtained onthebasis ofthe proposed strategy for0.5-pm CMOStechnology, reportminimization in averagepower consumption byabout36.1%, alongwitha substantial improvement inFoMtothetuneof nearly 45.7%,onanaverage.