Area Optimization of Arithmetic Units by Component Sharing for FPGAs (Abstract Only)

Floating point implementation has been a hot topic in recent FPGA research. This paper describes a method to optimize area of combined floating point and integer arithmetic unit through sharing the largest component in each operation on an FPGA. Specifically, the operations included are: addition, subtraction, multiplication, division, shift left/right, rotate left/right, as well as integer-to-floating-point and floating-point-to-integer conversion. The resource usage for the fused unit is compared with the segregated units that are multiplexed. Result shows a significant area reduction achieved using this technique with minimal performance penalty.