输入功率匹配范围为6.1 ~ 38.6 GHz,噪声系数最小值为1.9 dB,采用后门进行匹配的LNA

M. Radpour, L. Belostotski
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引用次数: 3

摘要

本文提出利用FDSOI晶体管的后门端进行输入功率匹配。该概念在22nm FDSOI低噪声放大器(LNA)上进行了实验验证。由于后门阻抗的实部,LNA| S11| < - 10-dB带宽从6.1扩展到38.6 GHz。此外,将输入同时应用于前端和后门终端,以及采用电流复用配置,可以增加LNA第一级的有效跨导,从而增加其增益并降低其输入参考噪声。因此,LNA能够实现12.2±3.4dB的增益,−13dBm的IP1dB,最小噪声系数为1.9 dB,功耗为7.8 mW,占用0.03 mm2的有源面积。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An LNA with Input Power Match from 6.1 to 38.6 GHz, the Noise-Figure Minimum of 1.9 dB, and Employing Back Gate for Matching
This paper proposes using the back-gate terminal of an FDSOI transistor for input power matching. This concept is experimentally demonstrated with a 22-nm FDSOI low-noise amplifier (LNA). Thanks to the real part of the back-gate impedance, the LNA| S11| < −10-dB bandwidth extends from 6.1 to 38.6 GHz. In addition, applying input to both the front-and back-gate terminals, as well as employing a current-reuse configuration, increases the effective transconductance of the LNA first stage, thereby increasing its gain and lowering its input-referred noise. As a result, the LNA is able to achieve 12.2 ± 3.4dB of gain, −13dBm of IP1dB, and a noise-figure minimum of 1.9 dB while consuming 7.8 mW of power and occupying 0.03-mm2 of active area.
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