深亚微米CMOS sram的传感设计问题

IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05) Pub Date : 2005-05-11 DOI:10.1109/ISVLSI.2005.67

A. Natarajan, V. Shankar, A. Maheshwari, W. Burleson

{"title":"深亚微米CMOS sram的传感设计问题","authors":"A. Natarajan, V. Shankar, A. Maheshwari, W. Burleson","doi":"10.1109/ISVLSI.2005.67","DOIUrl":null,"url":null,"abstract":"In this paper, solutions to memory design issues in nanometer CMOS are presented. First, a comparative study between various sense-amplifiers is presented in 70nm CMOS technology. Impact of process variation is studied on the performance of these sense-amplifiers. An improved bit-line leakage compensation scheme is proposed to ensure proper sensing in presence of leakage. Performance benefit of up to 68% can be obtained using this technique.","PeriodicalId":158790,"journal":{"name":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"Sensing design issues in deep submicron CMOS SRAMs\",\"authors\":\"A. Natarajan, V. Shankar, A. Maheshwari, W. Burleson\",\"doi\":\"10.1109/ISVLSI.2005.67\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, solutions to memory design issues in nanometer CMOS are presented. First, a comparative study between various sense-amplifiers is presented in 70nm CMOS technology. Impact of process variation is studied on the performance of these sense-amplifiers. An improved bit-line leakage compensation scheme is proposed to ensure proper sensing in presence of leakage. Performance benefit of up to 68% can be obtained using this technique.\",\"PeriodicalId\":158790,\"journal\":{\"name\":\"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-05-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISVLSI.2005.67\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVLSI.2005.67","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 9

摘要

本文提出了纳米CMOS中存储器设计问题的解决方案。首先，对70nm CMOS工艺下的各种传感器放大器进行了比较研究。研究了工艺变化对传感器性能的影响。提出了一种改进的位线泄漏补偿方案，以保证在存在泄漏的情况下也能正常检测。使用这种技术可以获得高达68%的性能优势。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Sensing design issues in deep submicron CMOS SRAMs

In this paper, solutions to memory design issues in nanometer CMOS are presented. First, a comparative study between various sense-amplifiers is presented in 70nm CMOS technology. Impact of process variation is studied on the performance of these sense-amplifiers. An improved bit-line leakage compensation scheme is proposed to ensure proper sensing in presence of leakage. Performance benefit of up to 68% can be obtained using this technique.

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IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05)

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