10位50MS/s流水线ADC的系统设计

2013 IEEE Workshop on Microelectronics and Electron Devices (WMED) Pub Date : 2013-04-12 DOI:10.1109/WMED.2013.6544508

Kehan Zhu, S. Balagopal, V. Saxena

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引用次数: 4

摘要

对一个10位50MS/s的流水线ADC进行了系统的设计分析。使用opamp共享技术，功耗大大降低。在130 nm CMOS工艺中进行仿真，在4.858 mhz 1-Vpp的正弦输入下，在50MS/s下实现了58.9dB的信噪比(SNR)， 9.3有效位数(ENOB)， 64dB无杂散动态范围(SFDR)， 1.2 v电源功耗小于24 mW。

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Systematic design of 10-bit 50MS/s pipelined ADC

A systematical design analysis of a 10-bit 50MS/s pipelined ADC is presented. With an opamp-sharing technique, the power consumption is reduced drastically. Simulated in a 130-nm CMOS process, it achieves a 58.9dB signal-to-noise ratio (SNR), a 9.3 effective number of bits (ENOB), 64dB spurious free dynamic range (SFDR) with a sinusoid input of 4.858-MHz 1-Vpp at 50MS/s, and consumes less than 24 mW from a 1.2-V supply.

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2013 IEEE Workshop on Microelectronics and Electron Devices (WMED)

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