Systemized software hardware partitioning algorithm for system on programmable chip to minimize logic power

To reduce the power consumption, in the literature, most works have focused in the field of batteries. However despite the progress made in this area, it is difficult to increase the battery capacity without increasing the weight, volume and price. To overcome such problems, in this paper we present a new approach based on hardware-software partitioning to reduce power consumption. In fact, in this paper we aim to solve the following issue: Given a control data flow graph a System on a Programmable Chip circuit; find a possible hardware-software partitioning of the graph on the System on a Programmable Chip in order to minimize the logic power and satisfying a temporal constraint.