8-Bit, 2 MSPS, 1.8 V Pipelined Analog-to-Digital Converter with Digital Error Correction Circuit for Data Communication

This paper presents the design of 8-bit pipelined analog-to-digital converter (ADC) with digital error correction circuit operates at the sampling frequency of 2 MHz. This work is implemented by 1.5-bit slice for the first 7-stages and followed by a simple flash ADC. Each 1.5-bit slice comprises a 2-bit comparator, a logic circuit and a residue amplifier. The residue amplifier consists of an operational amplifier with a gain-boosting technique to boost the overall open-loop DC gain. The technique incorporates isolation of the input differential pair by a pair of NMOS devices and a pair of OTA at the cascode stage of the core amplifier. Each stage provides 2-bit digital code that is aligned and added by the digital error correction circuit after all the operations complete. The conversion for the differential analog input is ranging from $\pm \mathbf{900\ mV}$. Post layout simulation results show that, the ADC is able to work functionally at 8-bit resolution with differential non-linearity (DNL) and integral non-linearity (INL) errors, $\pm 0.5$ and $\pm 2$ LSB, respectively. The ADC consumes 32 mW for the conversion. The dimension of the layout is 1800 $\mu \text{m}\times \mathbf{800}\ \mu \mathbf{m}$ and is fabricated using Silterra $\mathbf{0.18}\ \mu \mathbf{m}$ CMOS process technology.