A Circuit Implementation of Random Number Generator Utilizing Memristor Stochasticity

A random number generator is implemented utilizing the intrinsic stochasticity of memristor as a natural physical randomness source. The random bits are produced by cyclically switching the memristor and comparing the memristor resistive values in the high resistive state with the reference value, taking advantage of the more pronounced resistance variation in the high resistive state. Using the alternative voltage pulse scheme in the designed random number circuit, the biasness of the random numbers is largely alleviated, then the standard randomness test suite developed by NIST is used to validate the feasibility. Moreover, several memristors in parallel are considered to generate different frequency random number at the sacrifice of area overhead. The random number generation is simulated in the circuit simulated tool PSPICE. This approach improves the memristor-based stochastic circuit computer aided design.