W. Ahn, D. Jung, Y.K. Hong, H.H. Kim, Y. Kang, S.K. Kang, H.S. Kim, J. Kim, W. Jung, J. Jung, H. Ko, D. Choi, S.Y. Kim, E.S. Lee, J.Y. Kang, C. Wei, S.Y. Lee, K. A, H. Jung
{"title":"表征1T1C(1晶体管和1电容器)FRAM器件级耐用性的方法","authors":"W. Ahn, D. Jung, Y.K. Hong, H.H. Kim, Y. Kang, S.K. Kang, H.S. Kim, J. Kim, W. Jung, J. Jung, H. Ko, D. Choi, S.Y. Kim, E.S. Lee, J.Y. Kang, C. Wei, S.Y. Lee, K. A, H. Jung","doi":"10.1109/ISAF.2008.4693962","DOIUrl":null,"url":null,"abstract":"We present a mimicking methodology to describe device-level endurance in a 1T1C, 64 Mb FRAM (ferroelectric random access memory). Device-level endurance of FRAM must clarify all the issues raised from destructive read-out READ/WRITE. To explore endurance properties in a real-time operational situation, we have established a measurement set-up that covers asymmetric pulse chains corresponding to Data 1 (D1) and Data 0 (D0) READ/RESTORE over a frequency range from 1.0 to 7.7 MHz. The cycle-to-failure of 5.9 × 1024 cycles in an operational condition of 7.7 MHz and 85 °C, has been obtained from extrapolation to VDD = 2.0 V in a voltage acceleration. We compare testing results with those of D1¿D0 populations of bit-line potential.","PeriodicalId":228914,"journal":{"name":"2008 17th IEEE International Symposium on the Applications of Ferroelectrics","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A methodology to characterize device-level endurance in 1T1C (1-transistor and 1-capacitor) FRAM\",\"authors\":\"W. Ahn, D. Jung, Y.K. Hong, H.H. Kim, Y. Kang, S.K. Kang, H.S. Kim, J. Kim, W. Jung, J. Jung, H. Ko, D. Choi, S.Y. Kim, E.S. Lee, J.Y. Kang, C. Wei, S.Y. Lee, K. A, H. Jung\",\"doi\":\"10.1109/ISAF.2008.4693962\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a mimicking methodology to describe device-level endurance in a 1T1C, 64 Mb FRAM (ferroelectric random access memory). Device-level endurance of FRAM must clarify all the issues raised from destructive read-out READ/WRITE. To explore endurance properties in a real-time operational situation, we have established a measurement set-up that covers asymmetric pulse chains corresponding to Data 1 (D1) and Data 0 (D0) READ/RESTORE over a frequency range from 1.0 to 7.7 MHz. The cycle-to-failure of 5.9 × 1024 cycles in an operational condition of 7.7 MHz and 85 °C, has been obtained from extrapolation to VDD = 2.0 V in a voltage acceleration. We compare testing results with those of D1¿D0 populations of bit-line potential.\",\"PeriodicalId\":228914,\"journal\":{\"name\":\"2008 17th IEEE International Symposium on the Applications of Ferroelectrics\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-12-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 17th IEEE International Symposium on the Applications of Ferroelectrics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISAF.2008.4693962\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 17th IEEE International Symposium on the Applications of Ferroelectrics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISAF.2008.4693962","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A methodology to characterize device-level endurance in 1T1C (1-transistor and 1-capacitor) FRAM
We present a mimicking methodology to describe device-level endurance in a 1T1C, 64 Mb FRAM (ferroelectric random access memory). Device-level endurance of FRAM must clarify all the issues raised from destructive read-out READ/WRITE. To explore endurance properties in a real-time operational situation, we have established a measurement set-up that covers asymmetric pulse chains corresponding to Data 1 (D1) and Data 0 (D0) READ/RESTORE over a frequency range from 1.0 to 7.7 MHz. The cycle-to-failure of 5.9 × 1024 cycles in an operational condition of 7.7 MHz and 85 °C, has been obtained from extrapolation to VDD = 2.0 V in a voltage acceleration. We compare testing results with those of D1¿D0 populations of bit-line potential.
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