可编程逻辑阵列应用的基于rtd的可重构逻辑门

Donghyeok Bae, Jaehong Park, Maengkyu Kim, Y. Jeong, Kyounghoon Yang
{"title":"可编程逻辑阵列应用的基于rtd的可重构逻辑门","authors":"Donghyeok Bae, Jaehong Park, Maengkyu Kim, Y. Jeong, Kyounghoon Yang","doi":"10.1109/ICIPRM.2016.7528573","DOIUrl":null,"url":null,"abstract":"Summary form only given. Resonant-tunneling-diode (RTD) based reconfigurable logic gates have been designed and fabricated for RTD-based programmable logic array (PLA) applications. As PLA building blocks, two reconfigurable logic gates with three input terminals are proposed. The implemented gates show the reconfigurable functions of AND, OR, Majority, NOT, XOR, XNOR and 3-input XOR exploiting threshold characteristics of the RTD monostable-bistable transition logic element (MOBILE). The operation of the fabricated gates is successfully confirmed up to the clock frequency of 5 GHz. As for the full-adder topology, the number of devices in the proposed gate-based full-adder is less than a half of that in the conventional CMOS full-adder topology.","PeriodicalId":357009,"journal":{"name":"2016 Compound Semiconductor Week (CSW) [Includes 28th International Conference on Indium Phosphide & Related Materials (IPRM) & 43rd International Symposium on Compound Semiconductors (ISCS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"RTD-based reconfigurable logic gates for programmable logic array applications\",\"authors\":\"Donghyeok Bae, Jaehong Park, Maengkyu Kim, Y. Jeong, Kyounghoon Yang\",\"doi\":\"10.1109/ICIPRM.2016.7528573\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Summary form only given. Resonant-tunneling-diode (RTD) based reconfigurable logic gates have been designed and fabricated for RTD-based programmable logic array (PLA) applications. As PLA building blocks, two reconfigurable logic gates with three input terminals are proposed. The implemented gates show the reconfigurable functions of AND, OR, Majority, NOT, XOR, XNOR and 3-input XOR exploiting threshold characteristics of the RTD monostable-bistable transition logic element (MOBILE). The operation of the fabricated gates is successfully confirmed up to the clock frequency of 5 GHz. As for the full-adder topology, the number of devices in the proposed gate-based full-adder is less than a half of that in the conventional CMOS full-adder topology.\",\"PeriodicalId\":357009,\"journal\":{\"name\":\"2016 Compound Semiconductor Week (CSW) [Includes 28th International Conference on Indium Phosphide & Related Materials (IPRM) & 43rd International Symposium on Compound Semiconductors (ISCS)\",\"volume\":\"28 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-06-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 Compound Semiconductor Week (CSW) [Includes 28th International Conference on Indium Phosphide & Related Materials (IPRM) & 43rd International Symposium on Compound Semiconductors (ISCS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICIPRM.2016.7528573\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 Compound Semiconductor Week (CSW) [Includes 28th International Conference on Indium Phosphide & Related Materials (IPRM) & 43rd International Symposium on Compound Semiconductors (ISCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICIPRM.2016.7528573","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

只提供摘要形式。设计和制造了基于谐振隧道二极管(RTD)的可重构逻辑门,用于基于RTD的可编程逻辑阵列(PLA)。作为PLA的构建模块,提出了两个具有三个输入端的可重构逻辑门。所实现的门具有与、或、多数、非、异或、异或和3输入异或的可重构功能,利用了RTD单稳-双稳转换逻辑元件(MOBILE)的阈值特性。在时钟频率高达5 GHz的情况下,成功地证实了所制栅极的工作。对于全加法器拓扑,所提出的基于门的全加法器的器件数量少于传统CMOS全加法器拓扑的一半。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
RTD-based reconfigurable logic gates for programmable logic array applications
Summary form only given. Resonant-tunneling-diode (RTD) based reconfigurable logic gates have been designed and fabricated for RTD-based programmable logic array (PLA) applications. As PLA building blocks, two reconfigurable logic gates with three input terminals are proposed. The implemented gates show the reconfigurable functions of AND, OR, Majority, NOT, XOR, XNOR and 3-input XOR exploiting threshold characteristics of the RTD monostable-bistable transition logic element (MOBILE). The operation of the fabricated gates is successfully confirmed up to the clock frequency of 5 GHz. As for the full-adder topology, the number of devices in the proposed gate-based full-adder is less than a half of that in the conventional CMOS full-adder topology.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信