An efficient configuration unit design for VLIW based reconfigurable processors

The reconfigurable processors are the leading platforms being under consideration as a role model for reconfigurable computing systems. An application can be greatly accelerated by placing its computationally intensive portions of algorithms onto the reconfigurable platform. The gains are realized because the reconfigurable computing combines the benefits of both; the software and the ASIC solutions. However, the advantages of reconfigurable computing do not come without a cost. By requiring multiple reconfigurations to complete a computation, the time required to reconfigure the hardware significantly degrades the performance of such systems. The emerging reconfigurable architectures are focusing the efficient solutions for the configuration unit designs. Configuration unit is responsible for managing all activities relevant to the system configuration and hence it plays a vital role in reconfigurable processors. In this research paper an efficient configuration unit design has been presented for a VLIW based reconfigurable processor. The presented configuration unit is expected to be one of the most efficient design alternatives being available for reconfigurable processors. The presented configuration unit design is capable of loading the minimum configuration streams with the most optimal configuration overheads and hence it leads to a dramatic enhancement in the performance of reconfigurable processor.