HUnTer:利用soc级漏洞的底层触发硬件

S. Rajendran, Shams Tarek, Benjamin M Hicks, H. M. Kamali, Farimah Farahmandi, M. Tehranipoor
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引用次数: 2

摘要

片上系统(soc)变得越来越庞大和复杂,产生了新的威胁和漏洞,主要与系统级缺陷有关。然而,从SoC设计者的角度来看,由于缺乏决定性的(安全)需求和属性,系统级验证过程的违反可能导致利用硬件漏洞,因此没有得到全面的研究。为了对系统级属性进行更全面的验证,本文提出了HUnTer(硬件底层触发器),这是一个用于识别处理器单元(PU)上的指令集(序列)的框架,它揭示了底层硬件漏洞。HUnTer框架自动化了(i)威胁建模,(ii)基于威胁的形式化验证,(iii)生成反例,以及(iv)生成利用漏洞的代码片段。HUnTer框架还定义了一个安全覆盖度量(HUnT_Coverage)来度量所提议方法的性能和有效性。在基于risc - v的开源SoC架构上使用HUnTer框架,我们对Trust-HUB漏洞进行了广泛的案例研究,以证明所提出框架的有效性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
HUnTer: Hardware Underneath Trigger for Exploiting SoC-level Vulnerabilities
Systems-on-chip (SoCs) have become increasingly large and complex, resulting in new threats and vulnerabilities, mainly related to system-level flaws. However, the system-level verification process, whose violation may lead to exploiting a hardware vulnerability, is not studied comprehensively due to the lack of decisive (security) requirements and properties from the SoC designer's perspective. To enable a more comprehensive verification for system-level properties, this paper presents HUnTer (Hardware Underneath Trigger), a framework for identifying sets (sequences) of instructions at the processor unit (PU) that unveils the underneath hardware vulnerabilities. The HUnTer framework automates (i) threat modeling, (ii) threat-based formal verification, (iii) generation of counterexamples, and (iv) generation of snippet code for exploiting the vulnerability. The HUnTer framework also defines a security coverage metric (HUnT_Coverage) to measure the performance and efficacy of the proposed approach. Using the HUnTer framework on a RISC-V-based open-source SoC architecture, we conduct a wide variety of case studies of Trust-HUB vulnerabilities to demonstrate the high effectiveness of the proposed framework.
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