一种模拟辅助数字LDO，输出纹波0.37mV，负载电流范围5500x, 180nm CMOS

2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2022-10-28 DOI:10.1109/ICTA56932.2022.9963060

Luhua Lin, Bowen Wang, W. Rhee, Zhihua Wang

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引用次数: 0

摘要

本文提出了一种模拟辅助数字低差调节器(LDO)，该调节器采用δ σ调制器(DSM)和有限脉冲响应(FIR)滤波器来减小输出纹波。采用双模增益控制电压检测器(GCVD)和换挡算法，缩短了恢复时间。为了扩大负载电流范围，设计了指数比阵列。电荷泵(CP) LDO作为模拟辅助环路提高了瞬态性能。所提出的数字LDO在180nm CMOS上实现。当输出电压为0.9V时，在输入电压为1V时，最大负载电流为100mA，负载电流范围为5500x。负载电流从210mA到100mA变化时欠冲电压为78mV，输出纹波为0.37mV。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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An Analog-Assisted Digital LDO with 0.37mV Output Ripple and 5500x Load Current Range in 180nm CMOS

This paper presents an analog-assisted digital low dropout regulator (LDO) by adopting a delta sigma modulator (DSM) and a finite impulse response (FIR) filter for reduced output ripple. By employing a dual-mode gain-controlled voltage detector (GCVD) and a gear-shift algorithm, reduced recovery time is achieved. An exponential-ratio array (ERA) is designed to expand the load current range. A charge pump (CP) LDO as an analog-assisted loop enhances transient performance. The proposed digital LDO is implemented in 180nm CMOS. For an output voltage of 0.9V, a maximum load current of 100mA and 5500× load current range are achieved with an input voltage of 1V. The undershooting voltage is 78mV when the load current changes from 210mA to 100mA, and the output ripple is 0.37mV.

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2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)

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