S. Das, Tara Prasanna Dash, S. Dey, E. Mohapatra, J. Jena, C. K. Maiti
{"title":"纳米线场效应管中NBTI的降解和恢复","authors":"S. Das, Tara Prasanna Dash, S. Dey, E. Mohapatra, J. Jena, C. K. Maiti","doi":"10.1109/DEVIC.2019.8783566","DOIUrl":null,"url":null,"abstract":"Following the downscaling roadmap for planar MOSFETs, non-planar (3-D) multiple-gate architectures are becoming essential for ultimate scaling of CMOS devices. Negative bias temperature instability (NBTI) is one of the key device reliability issues which exhibit some different features at nanoscale. In this work, the NBTI reliability issues of p-channel gate-all-around silicon nanowire transistors (SNWTs) have been investigated. When stressed, NBTI behavior in SNWTs show fast initial degradation, quick degradation saturation and then a special recovery behavior.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"77 7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"NBTI Degradation and Recovery in Nanowire FETs\",\"authors\":\"S. Das, Tara Prasanna Dash, S. Dey, E. Mohapatra, J. Jena, C. K. Maiti\",\"doi\":\"10.1109/DEVIC.2019.8783566\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Following the downscaling roadmap for planar MOSFETs, non-planar (3-D) multiple-gate architectures are becoming essential for ultimate scaling of CMOS devices. Negative bias temperature instability (NBTI) is one of the key device reliability issues which exhibit some different features at nanoscale. In this work, the NBTI reliability issues of p-channel gate-all-around silicon nanowire transistors (SNWTs) have been investigated. When stressed, NBTI behavior in SNWTs show fast initial degradation, quick degradation saturation and then a special recovery behavior.\",\"PeriodicalId\":294095,\"journal\":{\"name\":\"2019 Devices for Integrated Circuit (DevIC)\",\"volume\":\"77 7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-03-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 Devices for Integrated Circuit (DevIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DEVIC.2019.8783566\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Devices for Integrated Circuit (DevIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DEVIC.2019.8783566","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Following the downscaling roadmap for planar MOSFETs, non-planar (3-D) multiple-gate architectures are becoming essential for ultimate scaling of CMOS devices. Negative bias temperature instability (NBTI) is one of the key device reliability issues which exhibit some different features at nanoscale. In this work, the NBTI reliability issues of p-channel gate-all-around silicon nanowire transistors (SNWTs) have been investigated. When stressed, NBTI behavior in SNWTs show fast initial degradation, quick degradation saturation and then a special recovery behavior.
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