{"title":"采用标准CMOS技术的高可靠性高压CMOS晶体管","authors":"W.F. Sun, L. Shi","doi":"10.1109/IPFA.2003.1222714","DOIUrl":null,"url":null,"abstract":"A novel high-reliability HV-CMOS (High Voltage CMOS) compatible with 0.6/spl mu/m rules standard Bulk-Silicon (BS) CMOS process was proposed. The reliability of the HV-CMOS is greatly improved by adding the p-well to HV-PMOS (High Voltage PMOS) for etching the unwanted thick-gate-oxide film and that to HV-DNMOS (High Voltage Double-Diffusion NMOS) for preventing punch-through. The breakdown voltage of the presented HV-CMOS exceeds 100 V, which can be used in power driver ICs, etc.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"High reliability HV-CMOS transistors in standard CMOS technology\",\"authors\":\"W.F. Sun, L. Shi\",\"doi\":\"10.1109/IPFA.2003.1222714\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel high-reliability HV-CMOS (High Voltage CMOS) compatible with 0.6/spl mu/m rules standard Bulk-Silicon (BS) CMOS process was proposed. The reliability of the HV-CMOS is greatly improved by adding the p-well to HV-PMOS (High Voltage PMOS) for etching the unwanted thick-gate-oxide film and that to HV-DNMOS (High Voltage Double-Diffusion NMOS) for preventing punch-through. The breakdown voltage of the presented HV-CMOS exceeds 100 V, which can be used in power driver ICs, etc.\",\"PeriodicalId\":266326,\"journal\":{\"name\":\"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-07-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IPFA.2003.1222714\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPFA.2003.1222714","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
摘要
提出了一种新的高可靠性HV-CMOS (High Voltage CMOS),兼容0.6/spl mu/m规则的标准Bulk-Silicon (BS) CMOS工艺。通过在HV-PMOS(高压PMOS)和HV-DNMOS(高压双扩散NMOS)上添加p阱来蚀刻不需要的厚栅氧化膜,从而大大提高了HV-CMOS的可靠性。所提出的高压cmos击穿电压超过100 V,可用于功率驱动ic等。
High reliability HV-CMOS transistors in standard CMOS technology
A novel high-reliability HV-CMOS (High Voltage CMOS) compatible with 0.6/spl mu/m rules standard Bulk-Silicon (BS) CMOS process was proposed. The reliability of the HV-CMOS is greatly improved by adding the p-well to HV-PMOS (High Voltage PMOS) for etching the unwanted thick-gate-oxide film and that to HV-DNMOS (High Voltage Double-Diffusion NMOS) for preventing punch-through. The breakdown voltage of the presented HV-CMOS exceeds 100 V, which can be used in power driver ICs, etc.