Asynchronous, Distributed Event Driven Simulation Algorithm for Execution of VHDL on Parallel Processors

This paper describes a new Asynchronous, Parallel, Event Driven Simulation algorithm with inconsistent event Preemption, P/sup 2/EDAS. P/sup 2/EDAS represents a significant advancement in distributed conservative digital circuit simulation algorithms in that it permits the use of any number of non-zero propagation delays for every path between the input and output of every hardware entity. P/sup 2/EDAS permits, accurate, concurrent, asynchronous, and efficient, i.e. deadlock free and null-message free, execution of sequential and combinatorial digital designs on parallel processors. It is a conservative algorithm in that only those output transitions, if any, are asserted at the output of a model following its execution, that are guaranteed correct. In addition, preemption of inconsistent events are allowed. P/sup 2/EDAS extends to any simulator based on high-level hardware description language. This paper presents a detailed description of the algorithm.