电路弹性加性攻击与应用程序,以确保计算安全

Daniel Genkin, Y. Ishai, M. Prabhakaran, A. Sahai, Eran Tromer
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引用次数: 96

摘要

我们研究了保护算术电路免受加性攻击的问题,加性攻击可以在电路中的每根导线上添加任意固定值。这将保护信息免受加法攻击的代数操作检测(AMD)代码的概念扩展到保护计算的AMD电路的概念。我们给出了这种AMD电路的构造:在有限域F上的任意算术电路C都可以转换成一个大小为O(|C|)的功能等效随机算术电路•C,该电路在以下意义上具有容错性。对于C导线上的任何加性攻击,其对C输出的影响可以通过仅对输入和输出进行加性攻击来模拟,最多可达到O(|C|/|F|)统计距离。给AMD代码一个小的防篡改编码器/解码器,输入和输出也可以得到保护。我们还提供了一种替代结构,适用于小领域(例如,保护布尔电路免受线切换攻击)。它使用一个小的防篡改解码器来确保,除非故障概率可以忽略不计,否则输出是正确的或检测到篡改。我们研究AMD电路的动机是简化和改进安全多方计算(MPC)协议。通常,保护MPC协议免受主动攻击者的攻击要比保护它们免受被动攻击者的攻击困难得多。我们观察到,在用于电路评估的简单被动安全MPC协议中,任何主动攻击者的影响都精确地对应于对原始电路导线的附加攻击。因此,为了在主动对手存在的情况下安全地评估电路C,将被动安全协议应用于C就足够了。我们使用这种方法来简化可行性结果,并在几个标准MPC模型中实现效率改进。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Circuits resilient to additive attacks with applications to secure computation
We study the question of protecting arithmetic circuits against additive attacks, which can add an arbitrary fixed value to each wire in the circuit. This extends the notion of algebraic manipulation detection (AMD) codes, which protect information against additive attacks, to that of AMD circuits which protect computation. We present a construction of such AMD circuits: any arithmetic circuit C over a finite field F can be converted into a functionally-equivalent randomized arithmetic circuit • C of size O(|C|) that is fault-tolerant in the following sense. For any additive attack on the wires of C, its effect on the output of C can be simulated, up to O(|C|/|F|) statistical distance, by an additive attack on just the input and output. Given a small tamper-proof encoder/decoder for AMD codes, the input and output can be protected as well. We also give an alternative construction, applicable to small fields (for example, to protect Boolean circuits against wire-toggling attacks). It uses a small tamper-proof decoder to ensure that, except with negligible failure probability, either the output is correct or tampering is detected. Our study of AMD circuits is motivated by simplifying and improving protocols for secure multiparty computation (MPC). Typically, securing MPC protocols against active adversaries is much more difficult than securing them against passive adversaries. We observe that in simple passive-secure MPC protocols for circuit evaluation, the effect of any active adversary corresponds precisely to an additive attack on the original circuit's wires. Thus, to securely evaluate a circuit C in the presence of active adversaries, it suffices to apply the passive-secure protocol to C. We use this methodology to simplify feasibility results and attain efficiency improvements in several standard MPC models.
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