{"title":"为DisplayPort 1.2设计的720Mbps快速辅助通道","authors":"Hyun-Bae Jin, Jong-Seok Han, Jin-Ku Kang","doi":"10.1109/SOCDC.2010.5682886","DOIUrl":null,"url":null,"abstract":"This paper presents the design of a fast auxiliary channel bus for DisplayPort 1.2 interface. The fast auxiliary channel supports Manchester transactions at 1Mbps and fast auxiliary transactions at 780Mbps. The Manchester transaction is used for managing the main link and auxiliary channel and the fast auxiliary transaction is for data transfer via the auxiliary channel. Simplified serial bus architecture is proposed to be implemented in fast auxiliary channel. The fast auxiliary channel is synthesized using a FPGA board and it operates at 72MHz to support 720Mbps.","PeriodicalId":380183,"journal":{"name":"2010 International SoC Design Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 720Mbps fast auxiliary channel design for DisplayPort 1.2\",\"authors\":\"Hyun-Bae Jin, Jong-Seok Han, Jin-Ku Kang\",\"doi\":\"10.1109/SOCDC.2010.5682886\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design of a fast auxiliary channel bus for DisplayPort 1.2 interface. The fast auxiliary channel supports Manchester transactions at 1Mbps and fast auxiliary transactions at 780Mbps. The Manchester transaction is used for managing the main link and auxiliary channel and the fast auxiliary transaction is for data transfer via the auxiliary channel. Simplified serial bus architecture is proposed to be implemented in fast auxiliary channel. The fast auxiliary channel is synthesized using a FPGA board and it operates at 72MHz to support 720Mbps.\",\"PeriodicalId\":380183,\"journal\":{\"name\":\"2010 International SoC Design Conference\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 International SoC Design Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCDC.2010.5682886\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 International SoC Design Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCDC.2010.5682886","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 720Mbps fast auxiliary channel design for DisplayPort 1.2
This paper presents the design of a fast auxiliary channel bus for DisplayPort 1.2 interface. The fast auxiliary channel supports Manchester transactions at 1Mbps and fast auxiliary transactions at 780Mbps. The Manchester transaction is used for managing the main link and auxiliary channel and the fast auxiliary transaction is for data transfer via the auxiliary channel. Simplified serial bus architecture is proposed to be implemented in fast auxiliary channel. The fast auxiliary channel is synthesized using a FPGA board and it operates at 72MHz to support 720Mbps.
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