{"title":"技术驱动的高层次综合","authors":"M. Joseph, N. Bhat, K. Sekaran","doi":"10.1109/ADCOM.2007.117","DOIUrl":null,"url":null,"abstract":"present High-Level Synthesis knowledgeable of the target Field Programmable Gate Array. All the functions of High-Level Syn- thesis become aware of target technology since parsing. It makes right inference of hardware, by attaching target technology specific attributes to the parse tree. This right inference will guide to generate optimized hardware. Keywords: High-Level Synthesis, Target Technology, At- tribute Grammars, Optimization, FPGA.","PeriodicalId":185608,"journal":{"name":"15th International Conference on Advanced Computing and Communications (ADCOM 2007)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Technology driven High-Level Synthesis\",\"authors\":\"M. Joseph, N. Bhat, K. Sekaran\",\"doi\":\"10.1109/ADCOM.2007.117\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"present High-Level Synthesis knowledgeable of the target Field Programmable Gate Array. All the functions of High-Level Syn- thesis become aware of target technology since parsing. It makes right inference of hardware, by attaching target technology specific attributes to the parse tree. This right inference will guide to generate optimized hardware. Keywords: High-Level Synthesis, Target Technology, At- tribute Grammars, Optimization, FPGA.\",\"PeriodicalId\":185608,\"journal\":{\"name\":\"15th International Conference on Advanced Computing and Communications (ADCOM 2007)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-12-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"15th International Conference on Advanced Computing and Communications (ADCOM 2007)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ADCOM.2007.117\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"15th International Conference on Advanced Computing and Communications (ADCOM 2007)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ADCOM.2007.117","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
present High-Level Synthesis knowledgeable of the target Field Programmable Gate Array. All the functions of High-Level Syn- thesis become aware of target technology since parsing. It makes right inference of hardware, by attaching target technology specific attributes to the parse tree. This right inference will guide to generate optimized hardware. Keywords: High-Level Synthesis, Target Technology, At- tribute Grammars, Optimization, FPGA.