{"title":"亚5nm节点无结多纳米片场效应管的自热效应","authors":"Nitish Kumar, Kanyakumari Ashok Bhinge, Sushil Kumar, Samaresh Das, Ankur Gupta, Pushpapraj Singh","doi":"10.1109/ICEE56203.2022.10117830","DOIUrl":null,"url":null,"abstract":"In this paper, the self-heating effect (SHE) is investigated in single nanosheet to stacked multi-nanosheet channels using the 3D electrothermal module of the Sentaurus TCAD simulation tool. The non-uniform lattice temperature (TL) distribution is observed in the junctionless multi-nanosheet FET. The device performance is enhanced by ~5% when the nanosheet is stacked from a single to three nanosheets, but the maximum lattice temperature (TLmax) also increases by ~66.8 K. The ON-current degradation and TLmax do not only define the device's thermal stability. Therefore, the thermal resistance is obtained by the slope of ΔTLmax and DC power curves, which reflects the low thermal resistance in the multi-nanosheet device. Furthermore, the TLmax of junctionless and inversion mode devices is compared at the same operational power. It is found ~ 100 K lower in junctionless devices due to weak lateral electric field intensity at the channel/drain interface.","PeriodicalId":281727,"journal":{"name":"2022 IEEE International Conference on Emerging Electronics (ICEE)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Self-Heating Effect in Sub-5nm Node Junctionless Multi-Nanosheet FET\",\"authors\":\"Nitish Kumar, Kanyakumari Ashok Bhinge, Sushil Kumar, Samaresh Das, Ankur Gupta, Pushpapraj Singh\",\"doi\":\"10.1109/ICEE56203.2022.10117830\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, the self-heating effect (SHE) is investigated in single nanosheet to stacked multi-nanosheet channels using the 3D electrothermal module of the Sentaurus TCAD simulation tool. The non-uniform lattice temperature (TL) distribution is observed in the junctionless multi-nanosheet FET. The device performance is enhanced by ~5% when the nanosheet is stacked from a single to three nanosheets, but the maximum lattice temperature (TLmax) also increases by ~66.8 K. The ON-current degradation and TLmax do not only define the device's thermal stability. Therefore, the thermal resistance is obtained by the slope of ΔTLmax and DC power curves, which reflects the low thermal resistance in the multi-nanosheet device. Furthermore, the TLmax of junctionless and inversion mode devices is compared at the same operational power. It is found ~ 100 K lower in junctionless devices due to weak lateral electric field intensity at the channel/drain interface.\",\"PeriodicalId\":281727,\"journal\":{\"name\":\"2022 IEEE International Conference on Emerging Electronics (ICEE)\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-12-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE International Conference on Emerging Electronics (ICEE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICEE56203.2022.10117830\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE International Conference on Emerging Electronics (ICEE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEE56203.2022.10117830","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Self-Heating Effect in Sub-5nm Node Junctionless Multi-Nanosheet FET
In this paper, the self-heating effect (SHE) is investigated in single nanosheet to stacked multi-nanosheet channels using the 3D electrothermal module of the Sentaurus TCAD simulation tool. The non-uniform lattice temperature (TL) distribution is observed in the junctionless multi-nanosheet FET. The device performance is enhanced by ~5% when the nanosheet is stacked from a single to three nanosheets, but the maximum lattice temperature (TLmax) also increases by ~66.8 K. The ON-current degradation and TLmax do not only define the device's thermal stability. Therefore, the thermal resistance is obtained by the slope of ΔTLmax and DC power curves, which reflects the low thermal resistance in the multi-nanosheet device. Furthermore, the TLmax of junctionless and inversion mode devices is compared at the same operational power. It is found ~ 100 K lower in junctionless devices due to weak lateral electric field intensity at the channel/drain interface.