晶圆级低压MOSFET的导通电阻测量

2023 35th International Conference on Microelectronic Test Structure (ICMTS) Pub Date : 2023-03-27 DOI:10.1109/ICMTS55420.2023.10094127

Kohei Oasa, T. Nishiwaki, T. Ohguro, Yasunobu Saito, Y. Kawaguchi

{"title":"晶圆级低压MOSFET的导通电阻测量","authors":"Kohei Oasa, T. Nishiwaki, T. Ohguro, Yasunobu Saito, Y. Kawaguchi","doi":"10.1109/ICMTS55420.2023.10094127","DOIUrl":null,"url":null,"abstract":"To accelerate the development of low voltage MOSFET, we designed a test element group pattern that enables on-resistance measurement at wafer level. We confirmed that the on-resistance can be measured at wafer level by optimizing the device size and contact method to eliminate the influence of parasitic resistance.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"On-Resistance Measurements of Low Voltage MOSFET at wafer level\",\"authors\":\"Kohei Oasa, T. Nishiwaki, T. Ohguro, Yasunobu Saito, Y. Kawaguchi\",\"doi\":\"10.1109/ICMTS55420.2023.10094127\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"To accelerate the development of low voltage MOSFET, we designed a test element group pattern that enables on-resistance measurement at wafer level. We confirmed that the on-resistance can be measured at wafer level by optimizing the device size and contact method to eliminate the influence of parasitic resistance.\",\"PeriodicalId\":275144,\"journal\":{\"name\":\"2023 35th International Conference on Microelectronic Test Structure (ICMTS)\",\"volume\":\"127 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-03-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2023 35th International Conference on Microelectronic Test Structure (ICMTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICMTS55420.2023.10094127\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMTS55420.2023.10094127","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

为了加速低压MOSFET的发展，我们设计了一种测试元件组模式，可以在晶圆级进行导通电阻测量。通过优化器件尺寸和接触方法，消除寄生电阻的影响，可以在晶圆级测量导通电阻。

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On-Resistance Measurements of Low Voltage MOSFET at wafer level

To accelerate the development of low voltage MOSFET, we designed a test element group pattern that enables on-resistance measurement at wafer level. We confirmed that the on-resistance can be measured at wafer level by optimizing the device size and contact method to eliminate the influence of parasitic resistance.

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2023 35th International Conference on Microelectronic Test Structure (ICMTS)

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