基于新的面向循环行处理策略的Saber KEM中高性能多项式乘法的FPGA实现

Jiafeng Xie, Pengzhou He, Chiou-Yng Lee
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引用次数: 7

摘要

量子技术的飞速发展引发了新一轮的后量子密码学(PQC)相关探索。关键封装机制(KEM) Saber是一种重要的基于格子模块的PQC,已被选为正在进行的美国国家标准与技术研究院(NIST)标准化过程中的PQC决赛选手之一。另一方面,然而,有效的硬件实现KEM军刀还没有很好地覆盖在文献中。因此,在本文中,我们提出了一种新的面向循环行处理(CROP)策略,用于有效地实现KEM Saber的关键算术运算,即多项式乘法。提出的工作包括三层相互依存的努力:(i)首先,我们将KEM Saber的主要操作制定为所需的数学形式,以进一步发展为基于CROP的算法,即基本版本和高级高速版本;(ii)然后,我们遵循提出的CROP策略,在一系列算法架构协同实现技术的帮助下,创新地将导出的两种算法转换为所需的多项式乘法结构;(iii)最后,详细的复杂性分析和实施结果表明,所提出的多项式乘法结构比最先进的解决方案具有更好的面积-时间复杂性。具体而言,现场可编程门阵列(FPGA)的实现结果表明,所提出的设计,例如,基本版本的面积延迟积(ADP)至少低于最佳竞争版本(Cyclone V器件)的11.2%。所提出的高性能多项式乘法器不仅具有高效的输出结果传递,而且具有CROP策略带来的低复杂度特征。本文的研究成果有望为KEM Saber的进一步开发和标准化进程提供有益的参考。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
CROP: FPGA Implementation of High-Performance Polynomial Multiplication in Saber KEM based on Novel Cyclic-Row Oriented Processing Strategy
The rapid advancement in quantum technology has initiated a new round of post-quantum cryptography (PQC) related exploration. The key encapsulation mechanism (KEM) Saber is an important module lattice-based PQC, which has been selected as one of the PQC finalists in the ongoing National Institute of Standards and Technology (NIST) standardization process. On the other hand, however, efficient hardware implementation of KEM Saber has not been well covered in the literature. In this paper, therefore, we propose a novel cyclic-row oriented processing (CROP) strategy for efficient implementation of the key arithmetic operation of KEM Saber, i.e., the polynomial multiplication. The proposed work consists of three layers of interdependent efforts: (i) first of all, we have formulated the main operation of KEM Saber into desired mathematical forms to be further developed into CROP based algorithms, i.e., the basic version and the advanced higher-speed version; (ii) then, we have followed the proposed CROP strategy to innovatively transfer the derived two algorithms into desired polynomial multiplication structures with the help of a series of algorithm-architecture co-implementation techniques; (iii) finally, detailed complexity analysis and implementation results have shown that the proposed polynomial multiplication structures have better area-time complexities than the state-of-the-art solutions. Specifically, the field-programmable gate array (FPGA) implementation results show that the proposed design, e.g., the basic version has at least less 11.2% area-delay product (ADP) than the best competing one (Cyclone V device). The proposed high-performance polynomial multipliers offer not only efficient operation for output results delivery but also possess low-complexity feature brought by CROP strategy. The outcome of this work is expected to provide useful references for further development and standardization process of KEM Saber.
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