最大限度地减少基于查找表的fpga

Kuang-Chien Chen, J. Cong
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引用次数: 6

摘要

现场可编程门阵列(FPGA)是一种重要的VLSI技术。针对fpga的合成提出了许多算法,但大多数算法都涉及到技术映射问题。作者提出了一种新的逻辑最小化算法MR (maximum reduction),用于FPGA网络的查找表最小化。获取有关如何使用网络重新合成技术删除查找表的信息。通过将查找表最小化问题表述为最大独立集问题,得到了全局最优解。实验结果表明,MR可以显著改善现有FPGA合成算法得到的设计。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Maximal reduction of lookup-table based FPGAs
Field programmable gate array (FPGA) is an important VLSI technology. Many algorithms have been proposed for the synthesis of FPGAs, but most of them concern issues in technology-mapping. The authors present a new logic minimization algorithm MR (maximal reduction) for the minimization of FPGA networks using lookup-tables. Information is obtained on how to remove the lookup tables by using network resynthesis techniques. Order-independent and global optimal results are obtained by formulating the lookup-table minimization problem as a maximum independent set problem. Experimental results show that MR can significantly improve the designs obtained by existing FPGA synthesis algorithms.<>
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