Hong Zhang, Dong Li, Qing Wang, Jie Zhang, Chong Li, Ruizhi Zhang
{"title":"一种用于超低功耗lsi的无电阻带隙参考元件,具有改进的PTAT发生器","authors":"Hong Zhang, Dong Li, Qing Wang, Jie Zhang, Chong Li, Ruizhi Zhang","doi":"10.1109/FTFC.2014.6828605","DOIUrl":null,"url":null,"abstract":"A resistor-less bandgap reference (BGR) for ultra-low power large-scale integrations (LSIs) is proposed in this paper. The BGR consists of a nano-ampere current reference circuit, a complementary-to-absolute-temperature (CTAT) voltage generator based on a diode connected MOSFET operating in subthreshold region, and a proportional-to-absolute-temperature (PTAT) voltage generator. A new topology that combines two mechanisms to generate PTAT voltage is proposed for the first stage of the PTAT generator, which can achieve higher slope in the voltage-temperature characteristics. Therefore, only 3 sub-stages are required in the PTAT generator, and both power dissipation and chip area can be reduced. The BGR is designed in a 0.35-μm CMOS process. Simulated results show that the BGR achieves a 1.1-V reference voltage with best temperature coefficient of 35 ppm/°C, while consuming only 40-nA under a 3.3 V power supply.","PeriodicalId":138166,"journal":{"name":"2014 IEEE Faible Tension Faible Consommation","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A resistor-less bandgap reference with improved PTAT generator for ultra-low-power LSIs\",\"authors\":\"Hong Zhang, Dong Li, Qing Wang, Jie Zhang, Chong Li, Ruizhi Zhang\",\"doi\":\"10.1109/FTFC.2014.6828605\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A resistor-less bandgap reference (BGR) for ultra-low power large-scale integrations (LSIs) is proposed in this paper. The BGR consists of a nano-ampere current reference circuit, a complementary-to-absolute-temperature (CTAT) voltage generator based on a diode connected MOSFET operating in subthreshold region, and a proportional-to-absolute-temperature (PTAT) voltage generator. A new topology that combines two mechanisms to generate PTAT voltage is proposed for the first stage of the PTAT generator, which can achieve higher slope in the voltage-temperature characteristics. Therefore, only 3 sub-stages are required in the PTAT generator, and both power dissipation and chip area can be reduced. The BGR is designed in a 0.35-μm CMOS process. Simulated results show that the BGR achieves a 1.1-V reference voltage with best temperature coefficient of 35 ppm/°C, while consuming only 40-nA under a 3.3 V power supply.\",\"PeriodicalId\":138166,\"journal\":{\"name\":\"2014 IEEE Faible Tension Faible Consommation\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-05-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 IEEE Faible Tension Faible Consommation\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/FTFC.2014.6828605\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE Faible Tension Faible Consommation","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FTFC.2014.6828605","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A resistor-less bandgap reference with improved PTAT generator for ultra-low-power LSIs
A resistor-less bandgap reference (BGR) for ultra-low power large-scale integrations (LSIs) is proposed in this paper. The BGR consists of a nano-ampere current reference circuit, a complementary-to-absolute-temperature (CTAT) voltage generator based on a diode connected MOSFET operating in subthreshold region, and a proportional-to-absolute-temperature (PTAT) voltage generator. A new topology that combines two mechanisms to generate PTAT voltage is proposed for the first stage of the PTAT generator, which can achieve higher slope in the voltage-temperature characteristics. Therefore, only 3 sub-stages are required in the PTAT generator, and both power dissipation and chip area can be reduced. The BGR is designed in a 0.35-μm CMOS process. Simulated results show that the BGR achieves a 1.1-V reference voltage with best temperature coefficient of 35 ppm/°C, while consuming only 40-nA under a 3.3 V power supply.