{"title":"180nm CMOS技术高增益米勒补偿高电源抑制运算放大器","authors":"Avishisht Kumar, P. Kumari, Imran Khan","doi":"10.1109/SMART50582.2020.9337073","DOIUrl":null,"url":null,"abstract":"In this paper the advantages of high supply rejection phenomenon in Opamp applications with Miller Compensation is evaluated. The operational amplifier is designed with 180 nm CMOS process ideally for temperature range of 25°C to 300°C. The Opamp is designed to have a DC gain of about 70dB and phase margin of 60°. The Miller compensation technique showed a reduction in the compensation capacitor size, means a smaller design area and improvement in the phase margin from the LHP zero. The operational amplifier has been designed and simulated Tanner EDA (SPICE Platform) in 180nm process technology.","PeriodicalId":129946,"journal":{"name":"2020 9th International Conference System Modeling and Advancement in Research Trends (SMART)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"High Gain Miller Compensated OpAmp with High Supply Rejection in 180 nm CMOS Technology\",\"authors\":\"Avishisht Kumar, P. Kumari, Imran Khan\",\"doi\":\"10.1109/SMART50582.2020.9337073\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper the advantages of high supply rejection phenomenon in Opamp applications with Miller Compensation is evaluated. The operational amplifier is designed with 180 nm CMOS process ideally for temperature range of 25°C to 300°C. The Opamp is designed to have a DC gain of about 70dB and phase margin of 60°. The Miller compensation technique showed a reduction in the compensation capacitor size, means a smaller design area and improvement in the phase margin from the LHP zero. The operational amplifier has been designed and simulated Tanner EDA (SPICE Platform) in 180nm process technology.\",\"PeriodicalId\":129946,\"journal\":{\"name\":\"2020 9th International Conference System Modeling and Advancement in Research Trends (SMART)\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-12-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 9th International Conference System Modeling and Advancement in Research Trends (SMART)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SMART50582.2020.9337073\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 9th International Conference System Modeling and Advancement in Research Trends (SMART)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMART50582.2020.9337073","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High Gain Miller Compensated OpAmp with High Supply Rejection in 180 nm CMOS Technology
In this paper the advantages of high supply rejection phenomenon in Opamp applications with Miller Compensation is evaluated. The operational amplifier is designed with 180 nm CMOS process ideally for temperature range of 25°C to 300°C. The Opamp is designed to have a DC gain of about 70dB and phase margin of 60°. The Miller compensation technique showed a reduction in the compensation capacitor size, means a smaller design area and improvement in the phase margin from the LHP zero. The operational amplifier has been designed and simulated Tanner EDA (SPICE Platform) in 180nm process technology.