FPGA implementation of reconfigurable architecture for half-band FIR filters

Dynamically reconfigurable filter with low complexity is need of hour today. FIR digital filter finds huge application in various disciplines because of stability and linear phase property. In this paper, recently discussed reconfigurable finite impulse response filter architecture is used to implement half-band filter. The proposed filter is employed to design an interpolator taking filter coefficients as inputs. These coefficients can be varied according to the specification without altering the underlying circuitry. While implementing polyphase components of interpolation filter the proposed architecture utilises farrow structure. We have used Xilinx's Artix7 family XC7A100T-3CSG324 field-programmable gate array to implement and test our architecture and synthesis results show that the proposed architecture offer enhanced speed when compared to other existing and proposed interpolators.