用于IEEE 802.11a/b/g WLAN的3.2至4 GHz, 0.25 /spl mu/m CMOS频率合成器

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) Pub Date : 2004-09-13 DOI:10.1109/ISSCC.2004.1332612

M. Terrovitis, M. Mack, K. Singh, M. Zargari

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引用次数: 28

摘要

完全集成的3.2至4 GHz频率合成器是IEEE 802.11a/b/g收发器的一部分，采用0.25 /spl mu/m标准CMOS技术实现。在10khz偏置时，相位噪声为-105 dBc/Hz，在5ghz发射机输出时，杂散低于-64 dBc。沉降时间小于150 /亩/秒。

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A 3.2 to 4 GHz, 0.25 /spl mu/m CMOS frequency synthesizer for IEEE 802.11a/b/g WLAN

A fully integrated 3.2 to 4 GHz frequency synthesizer, part of an IEEE 802.11a/b/g transceiver, is implemented in a 0.25 /spl mu/m standard CMOS technology. The phase noise is -105 dBc/Hz at 10 kHz offset, and the spurs are below -64 dBc when measured at the 5 GHz transmitter output. The settling time is less than 150 /spl mu/s.

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2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)

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