Evolution based automatic synthesis of analog integrated circuits

An automatic analog integrated circuit synthesis system driven by an evolutionary approach is presented. One of the novel features of this system is a high performance optimization algorithm based on the combination of evolutionary strategies and simulated annealing. Modeling of DC parameters is done via a fast DC simulator developed for this purpose whereas modeling of AC parameters is done either with user-defined equations or with neural-fuzzy performance models trained from SPICE simulations. Another novel feature of the system is the incorporation of matching properties of devices. The synthesis system has been tested on several independent examples. A prototype chip containing a synthesized circuit has been manufactured and measurement results have demonstrated the validity of the synthesis system also on silicon.