{"title":"基于risc - v的嵌入式处理器矢量运算单元的设计与实现","authors":"Zhao You, X. Zhang, Lin Han, Rongcai Zhao","doi":"10.1117/12.2680059","DOIUrl":null,"url":null,"abstract":"In order to address the growing demand for vector operations in embedded systems and the urgent need to enhance vector operations in embedded systems, this paper designs a 128-bit vector operation unit based on the open source RISC-V instruction set. In order to verify the correctness of the vector operation unit, we experimentally verify the vector operation unit in the ModelSim simulation environment, and all modules meet the correctness requirements. In addition, we integrated the vector operation unit with the open-source processor Hummingbird E203 and tested it on a 16MHz FPGA development board. The results show a 1.2 times performance improvement of the demo application compared to the scalar processor.","PeriodicalId":201466,"journal":{"name":"Symposium on Advances in Electrical, Electronics and Computer Engineering","volume":"61 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design and implementation of RISC-V-based vector operation unit for embedded processor\",\"authors\":\"Zhao You, X. Zhang, Lin Han, Rongcai Zhao\",\"doi\":\"10.1117/12.2680059\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In order to address the growing demand for vector operations in embedded systems and the urgent need to enhance vector operations in embedded systems, this paper designs a 128-bit vector operation unit based on the open source RISC-V instruction set. In order to verify the correctness of the vector operation unit, we experimentally verify the vector operation unit in the ModelSim simulation environment, and all modules meet the correctness requirements. In addition, we integrated the vector operation unit with the open-source processor Hummingbird E203 and tested it on a 16MHz FPGA development board. The results show a 1.2 times performance improvement of the demo application compared to the scalar processor.\",\"PeriodicalId\":201466,\"journal\":{\"name\":\"Symposium on Advances in Electrical, Electronics and Computer Engineering\",\"volume\":\"61 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-05-31\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Symposium on Advances in Electrical, Electronics and Computer Engineering\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1117/12.2680059\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Symposium on Advances in Electrical, Electronics and Computer Engineering","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1117/12.2680059","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design and implementation of RISC-V-based vector operation unit for embedded processor
In order to address the growing demand for vector operations in embedded systems and the urgent need to enhance vector operations in embedded systems, this paper designs a 128-bit vector operation unit based on the open source RISC-V instruction set. In order to verify the correctness of the vector operation unit, we experimentally verify the vector operation unit in the ModelSim simulation environment, and all modules meet the correctness requirements. In addition, we integrated the vector operation unit with the open-source processor Hummingbird E203 and tested it on a 16MHz FPGA development board. The results show a 1.2 times performance improvement of the demo application compared to the scalar processor.