A novel design of low power FinFET adiabatic circuits for VLSI applications

The scaling of the commercially popular bulk MOSFETS faces two major challenges as minimization of leakage current and reduction in device to device variability to increase yield. In this paper, an improved low power adiabatic logic based on FinFET has been proposed. FinFET posse's lower leakage current and high on-state current which increase the performance and save area compared to CMOS adiabatic logic. For validating our idea we design power gated adiabatic inverter circuits using techniques like 2N2N2P, DCPAL, PFAL, IPAL and Fin SAL. We have also designed Fin SAL based AND/NAND and XOR/XNOR gates. The test circuit has been demonstrated based on 32-nm FinFET Predictive Technology Model. The simulation results show that adiabatic circuit based on FinFET devices achieve power reduction.