{"title":"Epoch IC设计系统响应VHDL/VITAL要求","authors":"F. Hinchliffe","doi":"10.1109/NORTHC.1994.643364","DOIUrl":null,"url":null,"abstract":"This paper describes the impact that recent changes to VHDL in the area of ASIC modeling will have upon the Epoch IC design system. Epoch delay modeling and simulation support have been implemented to provide for the critically important needs of post-layout simulation.","PeriodicalId":218454,"journal":{"name":"Proceedings of NORTHCON '94","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Epoch IC design system response to VHDL/VITAL requirements\",\"authors\":\"F. Hinchliffe\",\"doi\":\"10.1109/NORTHC.1994.643364\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the impact that recent changes to VHDL in the area of ASIC modeling will have upon the Epoch IC design system. Epoch delay modeling and simulation support have been implemented to provide for the critically important needs of post-layout simulation.\",\"PeriodicalId\":218454,\"journal\":{\"name\":\"Proceedings of NORTHCON '94\",\"volume\":\"20 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-10-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of NORTHCON '94\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NORTHC.1994.643364\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of NORTHCON '94","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NORTHC.1994.643364","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Epoch IC design system response to VHDL/VITAL requirements
This paper describes the impact that recent changes to VHDL in the area of ASIC modeling will have upon the Epoch IC design system. Epoch delay modeling and simulation support have been implemented to provide for the critically important needs of post-layout simulation.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
