Kohonen自组织神经网络并行协处理器

J. Saarinen, Martti Lindroos, J. Tomberg, K. Kaski
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引用次数: 5

摘要

描述了一种新的自组织特征映射算法的高效集成电路实现。全数字硬件设计用于高速并行处理和模块化可扩展性。硬件实现作为一个神经协处理器,使用同步、位串行算法。它包括执行欧几里得距离计算、最小距离搜索、内存控制和更新功能的功能单元。芯片上的学习有助于完全自主操作。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Parallel coprocessor for Kohonen's self-organizing neural network
A new efficient integrated circuit implementation of the Self-Organising Feature Map algorithm is described. The fully digital hardware is designed for high speed parallel processing and modular expandability. The hardware implementation acts as a neural coprocessor which uses synchronous, bit-serial arithmetic. It includes functional units which perform the Euclidean distance computation, the minimum distance search, the memory controlling, and the updating function. The on-chip learning facilitates fully autonomous operation.<>
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