Taehoon Kim, Sunkwon Kim, J. Woo, Hyongmin Lee, Suhwan Kim
{"title":"一个9位，110毫秒/秒的流水线sar ADC，采用时间交错技术和共享比较器","authors":"Taehoon Kim, Sunkwon Kim, J. Woo, Hyongmin Lee, Suhwan Kim","doi":"10.1109/SOCC.2015.7406934","DOIUrl":null,"url":null,"abstract":"A 9-bit 110-MS/s pipelined-SAR ADC is proposed. To alleviate the design tradeoff between conversion rate and power consumption, the design adopts a voltage-mode open-loop amplifier and a time-interleaved SAR architecture with comparator sharing. The ADC simulated in a 65-nm CMOS technology achieves an ENOB of 8.63 bits near the Nyquist input frequency at the sampling rate of 110MS/s. The power consumption is 7.9mW, resulting in 181.3fJ/conversion-step of Figure of Merit (FoM).","PeriodicalId":329464,"journal":{"name":"2015 28th IEEE International System-on-Chip Conference (SOCC)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A 9-bit, 110-MS/s pipelined-SAR ADC using time-interleaved technique with shared comparator\",\"authors\":\"Taehoon Kim, Sunkwon Kim, J. Woo, Hyongmin Lee, Suhwan Kim\",\"doi\":\"10.1109/SOCC.2015.7406934\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 9-bit 110-MS/s pipelined-SAR ADC is proposed. To alleviate the design tradeoff between conversion rate and power consumption, the design adopts a voltage-mode open-loop amplifier and a time-interleaved SAR architecture with comparator sharing. The ADC simulated in a 65-nm CMOS technology achieves an ENOB of 8.63 bits near the Nyquist input frequency at the sampling rate of 110MS/s. The power consumption is 7.9mW, resulting in 181.3fJ/conversion-step of Figure of Merit (FoM).\",\"PeriodicalId\":329464,\"journal\":{\"name\":\"2015 28th IEEE International System-on-Chip Conference (SOCC)\",\"volume\":\"104 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 28th IEEE International System-on-Chip Conference (SOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCC.2015.7406934\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 28th IEEE International System-on-Chip Conference (SOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC.2015.7406934","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 9-bit, 110-MS/s pipelined-SAR ADC using time-interleaved technique with shared comparator
A 9-bit 110-MS/s pipelined-SAR ADC is proposed. To alleviate the design tradeoff between conversion rate and power consumption, the design adopts a voltage-mode open-loop amplifier and a time-interleaved SAR architecture with comparator sharing. The ADC simulated in a 65-nm CMOS technology achieves an ENOB of 8.63 bits near the Nyquist input frequency at the sampling rate of 110MS/s. The power consumption is 7.9mW, resulting in 181.3fJ/conversion-step of Figure of Merit (FoM).
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